Commit fe3962b
Implement RISCV Translation (#5)
* instruction: split arm, riscv opcodes and add registers
* translate: add minimal riscv translation map
* meta: rename `test/` -> `tests/`
* test imports
* instruction: specify arguments to RISC-V ops
* wip translations
* map_val empty
* more translations + builds now
* test: run translation from RISCV to ARM enums
* map_register use helpers
* update calls to map_register with widths
* fix move of width values
* map width
* translate: `map_register_name` with semantic meanings
Corrected the translation between registers for our 64 bit architectures.
* map width
* starting instruction encoding
* have assembly output now
* patched and assembled aarch64 add
* fix patched add example
* fixed width/segfault issues
* call syscall
* merge and working print
* print and echo tests
* basic control flow
* fix count to 5 test
* meta: add final documentation
* tests badge
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Co-authored-by: Anthony Tarbinian <atar137h@gmail.com>
Co-authored-by: David Tran <tr.davidt@gmail.com>1 parent 7577fe8 commit fe3962b
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lines changed- src
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- riscv
- test
- binaries
31 files changed
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