metrics.csv

design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/openlane/designs/audio_soc,audio_soc_top,initial_run,flow completed,0h5m19s0ms,0h4m31s0ms,103875.65167815035,0.063730045425,51937.82583907517,52.04,-1,687.3,2691,0,0,0,0,0,0,0,2,2,0,-1,-1,80652,21857,0.0,-1,-1,-1,0.0,0.0,-1,-1,-1,0.0,47612648.0,0.0,35.44,34.62,10.7,15.05,-1,2881,4749,159,2013,0,0,0,3367,26,47,50,95,279,131,42,948,574,575,23,1969,792,1,1264,3310,7336,55200.4416,-1,-1,-1,0.00371,0.00348,1.75e-08,-1,-1,-1,6.45,20.0,50.0,20.0,1,50,160,160,0.3,1,10,0.65,0,sky130_fd_sc_hd,DELAY 0