diff --git a/__pycache__/test_packet_handler.cpython-312-pytest-8.0.0.pyc b/__pycache__/test_packet_handler.cpython-312-pytest-8.0.0.pyc new file mode 100644 index 0000000..dfd8cc0 Binary files /dev/null and b/__pycache__/test_packet_handler.cpython-312-pytest-8.0.0.pyc differ diff --git a/packet_handler.v b/packet_handler.v index cefbc0c..b97f28c 100644 --- a/packet_handler.v +++ b/packet_handler.v @@ -1,58 +1,194 @@ module packet_handler( /* clocks and resets */ - i_clk, - i_rst_n, + input i_clk, + input i_rst_n, /* input signals */ - i_data, - i_valid, - i_ready, - i_last, + input [31:0] i_data, + input i_valid, + input i_last, + input i_ready, /* output signals */ - o_data, - o_ready, - o_valid, - o_packetLost + output reg [295:0] o_data, + output o_ready, + output reg o_valid, + output o_packetLost ); - /* clocks and resets */ - input i_clk; - input i_rst_n; - /* input signals */ - input [31:0] i_data; - input i_valid; - input i_ready; - input i_last; - /* output signals */ - output reg [295:0] o_data; - output reg o_ready; - output reg o_valid; - output o_packetLost; - /* internal signals */ - /* header format values */ - reg [15:0] msgLength; - reg [15:0] streamId; - reg [31:0] seqNumber; - /* using unpacked array to track seqNumber based on streamId - using 32 bits to store seqNumber and 32 elements for each streamId */ - reg [31:0] packetTracker [31:0]; - /* serial to paraller shift register */ + /* FIFO instantiation */ + reg [32:0] fifo_mem [0:255]; + reg [7:0] fifo_wr_ptr; + reg [7:0] fifo_rd_ptr; + reg [8:0] fifo_count; + + wire fifo_full = (fifo_count == 9'd256); + wire fifo_empty = (fifo_count == 9'd0); + + wire fifo_wr_en = i_valid && !fifo_full; + assign o_ready = !fifo_full; + + wire fifo_valid = !fifo_empty; + wire [31:0] fifo_data = fifo_mem[fifo_rd_ptr][31:0]; + wire fifo_last = fifo_mem[fifo_rd_ptr][32]; + + wire fifo_rd_en; + + always @(posedge i_clk or negedge i_rst_n) begin + if (!i_rst_n) begin + fifo_wr_ptr <= 8'd0; + fifo_rd_ptr <= 8'd0; + fifo_count <= 9'd0; + end else begin + case ({fifo_wr_en, fifo_rd_en}) + 2'b10: fifo_count <= fifo_count + 1; + 2'b01: fifo_count <= fifo_count - 1; + default: fifo_count <= fifo_count; + endcase + + if (fifo_wr_en) begin + fifo_mem[fifo_wr_ptr] <= {i_last, i_data}; + fifo_wr_ptr <= fifo_wr_ptr + 1; + end + + if (fifo_rd_en) begin + fifo_rd_ptr <= fifo_rd_ptr + 1; + end + end + end + + /* Input tracking logic for o_packetLost */ + reg [1:0] in_state; + localparam IN_W1 = 2'd0; + localparam IN_W2 = 2'd1; + localparam IN_DATA = 2'd2; + + /* verilator lint_off UNUSEDSIGNAL */ + reg [15:0] in_streamId; + /* verilator lint_on UNUSEDSIGNAL */ + reg in_packetLost; + integer i; + + assign o_packetLost = in_packetLost; + +`ifdef SYNTHESIS + // BRAM instance for Synthesis + // Note: BRAM inference requires synchronous read and write + reg [31:0] packetTracker [0:31]; + reg [31:0] packetTracker_read_data; + + // Read logic using synchronous read to properly infer BRAM. + // Address is generated in IN_W1 when fifo_wr_en is high. + wire [4:0] stream_idx_w1 = i_data[12:8] - 5'd1; + wire [4:0] stream_idx_w2 = in_streamId[4:0] - 5'd1; + + always @(posedge i_clk) begin + // Read during IN_W1 so data is available in IN_W2 + if (fifo_wr_en && in_state == IN_W1) begin + packetTracker_read_data <= packetTracker[stream_idx_w1]; + end + + // Write during IN_W2 + if (fifo_wr_en && in_state == IN_W2) begin + packetTracker[stream_idx_w2] <= packetTracker_read_data + 1; + end + end + + always @(posedge i_clk or negedge i_rst_n) begin + if (!i_rst_n) begin + in_state <= IN_W1; + in_streamId <= 16'd0; + in_packetLost <= 1'b0; + end else begin + in_packetLost <= 1'b0; + if (fifo_wr_en) begin + case (in_state) + IN_W1: begin + in_streamId <= {i_data[7:0], i_data[15:8]}; + in_state <= IN_W2; + end + IN_W2: begin + if ((packetTracker_read_data + 1) != {i_data[7:0], i_data[15:8], i_data[23:16], i_data[31:24]}) begin + in_packetLost <= 1'b1; + end + if (i_last) begin + in_state <= IN_W1; + end else begin + in_state <= IN_DATA; + end + end + IN_DATA: begin + if (i_last) begin + in_state <= IN_W1; + end + end + default: in_state <= IN_W1; + endcase + end + end + end +`else + // Original Logic for simulation + reg [31:0] packetTracker [31:0]; + + wire [4:0] stream_idx_w2 = in_streamId[4:0] - 5'd1; + + always @(posedge i_clk or negedge i_rst_n) begin + if (!i_rst_n) begin + in_state <= IN_W1; + in_streamId <= 16'd0; + in_packetLost <= 1'b0; + for (i = 0; i < 32; i = i + 1) begin + packetTracker[i] <= 32'b0; + end + end else begin + in_packetLost <= 1'b0; + if (fifo_wr_en) begin + case (in_state) + IN_W1: begin + in_streamId <= {i_data[7:0], i_data[15:8]}; + in_state <= IN_W2; + end + IN_W2: begin + packetTracker[stream_idx_w2] <= packetTracker[stream_idx_w2] + 1; + if ((packetTracker[stream_idx_w2] + 1) != {i_data[7:0], i_data[15:8], i_data[23:16], i_data[31:24]}) begin + in_packetLost <= 1'b1; + end + if (i_last) begin + in_state <= IN_W1; + end else begin + in_state <= IN_DATA; + end + end + IN_DATA: begin + if (i_last) begin + in_state <= IN_W1; + end + end + default: in_state <= IN_W1; + endcase + end + end + end +`endif + + /* Internal FSM */ + /* verilator lint_off UNUSEDSIGNAL */ reg [15:0] msgLength; /* verilator lint_on UNUSEDSIGNAL */ + /* verilator lint_off UNUSEDSIGNAL */ reg [15:0] streamId; /* verilator lint_on UNUSEDSIGNAL */ + /* verilator lint_off UNUSEDSIGNAL */ reg [31:0] seqNumber; /* verilator lint_on UNUSEDSIGNAL */ reg [295:0] shiftReg; - /* state and next state registers for FSM */ reg [3:0] state; reg [3:0] next_state; - /* registers to help generate o_packLost pulse */ - reg o_packetLostReg; - reg o_packetLostReg_d; - /* one-hot encoding for FSM states*/ localparam IDLE = 4'b0001; localparam HEADER = 4'b0010; localparam DATA = 4'b0100; localparam DONE = 4'b1000; - /* FSM initialization - sequential block - state registers definition */ + assign fifo_rd_en = ((state == IDLE) && fifo_valid) || + ((state == HEADER) && fifo_valid) || + ((state == DATA) && fifo_valid); + always @(posedge i_clk or negedge i_rst_n) begin if (!i_rst_n) begin state <= IDLE; @@ -61,34 +197,30 @@ module packet_handler( end end - /* FSM state logic - combinational block - next state logic */ always @(*) begin case (state) IDLE: begin - /* transmitter asserts i_valid, data transaction - can be initiated since o_ready is high */ - if (i_valid) begin + if (fifo_valid) begin next_state = HEADER; end else begin next_state = IDLE; end end - /* extra state to receive and store the next 4 bytes - of header */ HEADER: begin - /* unconditional transition to next state */ - next_state = DATA; + if (fifo_valid) begin + next_state = DATA; + end else begin + next_state = HEADER; + end end DATA: begin - /* transmitter asserts i_last so its done sending data */ - if (i_last) begin + if (fifo_valid && fifo_last) begin next_state = DONE; end else begin next_state = DATA; end end DONE: begin - /* receiver asserts i_ready, data can be sent */ if (i_ready) begin next_state = IDLE; end else begin @@ -101,61 +233,41 @@ module packet_handler( endcase end - //FSM output logic - sequential block always @(posedge i_clk or negedge i_rst_n) begin if (!i_rst_n) begin - o_ready <= 1'b1; o_valid <= 1'b0; end else begin case (state) IDLE: begin - /* FPGA is ready to receive data from transmitter */ - o_ready <= 1'b1; o_valid <= 1'b0; end HEADER: begin - /* FPGA is ready to receive data from transmitter */ - o_ready <= 1'b1; o_valid <= 1'b0; end DATA: begin - /* FPGA is ready to receive data from transmitter */ - o_ready <= 1'b1; - /* transmitter has sent all data, FPGA is ready to - send data to receiver */ - if (i_last) begin + if (fifo_valid && fifo_last) begin o_valid <= 1'b1; end else begin o_valid <= 1'b0; end end DONE: begin - /* receiver is ready to receive data, FPGA can go - back to being ready to receive data from transmitter*/ if (i_ready) begin o_valid <= 1'b0; - o_ready <= 1'b1; end else begin o_valid <= 1'b1; - o_ready <= 1'b0; end end default: begin - o_ready <= 1'b0; o_valid <= 1'b0; end endcase end end - /* serial to parallel data with shift register - and logic to extract header information - the indexes on i_data signal are based on the fact - that bytes are stored in little endian for each field - of the header*/ always @(posedge i_clk or negedge i_rst_n) begin if (!i_rst_n) begin - o_data <= 32'b0; + o_data <= 296'b0; msgLength <= 16'b0; streamId <= 16'b0; seqNumber <= 32'b0; @@ -164,29 +276,25 @@ module packet_handler( case (state) IDLE: begin shiftReg <= 296'b0; - if (i_valid && o_ready) begin - /* extract first 4 bytes of header fields - stored in little endian */ - msgLength <= {i_data[23:16], i_data[31:24]}; - streamId <= {i_data[7:0], i_data[15:8]}; + if (fifo_valid) begin + msgLength <= {fifo_data[23:16], fifo_data[31:24]}; + streamId <= {fifo_data[7:0], fifo_data[15:8]}; end else begin msgLength <= 16'b0; streamId <= 16'b0; end end HEADER: begin - /* extract last 4 bytes of header field - sotred in little endian */ - seqNumber <= {i_data[7:0], i_data[15:8], i_data[23:16], i_data[31:24]}; + if (fifo_valid) begin + seqNumber <= {fifo_data[7:0], fifo_data[15:8], fifo_data[23:16], fifo_data[31:24]}; + end end DATA: begin - /* shifting 32 bits of incoming data into register */ - shiftReg <= {shiftReg[263:0], i_data}; + if (fifo_valid) begin + shiftReg <= {shiftReg[263:0], fifo_data}; + end end DONE: begin - /* transimitter is done sending data - data can be outputed to receiver as long as - receiver is ready */ if (i_ready) begin o_data <= shiftReg; end else begin @@ -194,7 +302,7 @@ module packet_handler( end end default: begin - o_data <= 32'b0; + o_data <= 296'b0; msgLength <= 16'b0; streamId <= 16'b0; seqNumber <= 32'b0; @@ -204,58 +312,4 @@ module packet_handler( end end - /* Lost packet detection logic */ - integer i; - always @(posedge i_clk or negedge i_rst_n) begin - if (!i_rst_n) begin - /* initializing packetTracker to 0s */ - for (i = 0; i < 32; i = i + 1) begin - packetTracker[i] <= 32'b0; - end - end else begin - case (state) - IDLE: begin - o_packetLostReg <= 1'b0; - end - HEADER: begin - /* updating internal counter for incoming streamId - streamId range is 1-32 and index range is 0-31 */ - o_packetLostReg <= 1'b0; - packetTracker[streamId-1] <= packetTracker[streamId-1]+1; - end - DATA: begin - /* comparing internal counter for incoming streamId - with incoming seqNumber and asserting o_packetLostReg - if it is not the same */ - if (packetTracker[streamId-1] == seqNumber) begin - o_packetLostReg <= 1'b0; - end else begin - o_packetLostReg <= 1'b1; - end - end - DONE: begin - o_packetLostReg <= 1'b0; - end - default: begin - for (i = 0; i < 32; i = i + 1) begin - packetTracker[i] <= 32'b0; - end - end - endcase - end - end - - /* o_packetLost needs to be a pulse so an - edge detector is used to help generate it */ - always @(posedge i_clk or negedge i_rst_n) begin - if (!i_rst_n) begin - o_packetLostReg_d <= 1'b0; - end else begin - o_packetLostReg_d <= o_packetLostReg; - end - end - - /* generation of o_packetLost pulse from regisered signals */ - assign o_packetLost = o_packetLostReg & ~o_packetLostReg_d; - -endmodule \ No newline at end of file +endmodule diff --git a/results.xml b/results.xml new file mode 100644 index 0000000..204475b --- /dev/null +++ b/results.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/sim_build/cmds.f b/sim_build/cmds.f new file mode 100644 index 0000000..3e26e00 --- /dev/null +++ b/sim_build/cmds.f @@ -0,0 +1 @@ ++timescale+1ns/1ps diff --git a/sim_build/sim.vvp b/sim_build/sim.vvp new file mode 100755 index 0000000..6331e88 --- /dev/null +++ b/sim_build/sim.vvp @@ -0,0 +1,606 @@ +#! /usr/bin/vvp +:ivl_version "12.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi"; +S_0x55e26aed54c0 .scope package, "$unit" "$unit" 2 1; + .timescale -9 -12; +S_0x55e26aed5650 .scope module, "packet_handler" "packet_handler" 3 1; + .timescale -9 -12; + .port_info 0 /INPUT 1 "i_clk"; + .port_info 1 /INPUT 1 "i_rst_n"; + .port_info 2 /INPUT 32 "i_data"; + .port_info 3 /INPUT 1 "i_valid"; + .port_info 4 /INPUT 1 "i_last"; + .port_info 5 /INPUT 1 "i_ready"; + .port_info 6 /OUTPUT 296 "o_data"; + .port_info 7 /OUTPUT 1 "o_ready"; + .port_info 8 /OUTPUT 1 "o_valid"; + .port_info 9 /OUTPUT 1 "o_packetLost"; +P_0x55e26af35990 .param/l "DATA" 1 3 185, C4<0100>; +P_0x55e26af359d0 .param/l "DONE" 1 3 186, C4<1000>; +P_0x55e26af35a10 .param/l "HEADER" 1 3 184, C4<0010>; +P_0x55e26af35a50 .param/l "IDLE" 1 3 183, C4<0001>; +P_0x55e26af35a90 .param/l "IN_DATA" 1 3 64, C4<10>; +P_0x55e26af35ad0 .param/l "IN_W1" 1 3 62, C4<00>; +P_0x55e26af35b10 .param/l "IN_W2" 1 3 63, C4<01>; +o0x7fc8cdc2f708 .functor BUFZ 1, C4; HiZ drive +L_0x55e26af072e0 .functor AND 1, o0x7fc8cdc2f708, L_0x55e26af67320, C4<1>, C4<1>; +L_0x55e26af0a240 .functor BUFZ 1, v0x55e26af562f0_0, C4<0>, C4<0>, C4<0>; +L_0x55e26af67de0 .functor AND 1, L_0x55e26af68010, L_0x55e26af67530, C4<1>, C4<1>; +L_0x55e26af0a8e0 .functor AND 1, L_0x55e26af68250, L_0x55e26af67530, C4<1>, C4<1>; +L_0x55e26af0d490 .functor OR 1, L_0x55e26af67de0, L_0x55e26af0a8e0, C4<0>, C4<0>; +L_0x55e26af68630 .functor AND 1, L_0x55e26af684b0, L_0x55e26af67530, C4<1>, C4<1>; +L_0x55e26af68730 .functor OR 1, L_0x55e26af0d490, L_0x55e26af68630, C4<0>, C4<0>; +L_0x7fc8cdbe6018 .functor BUFT 1, C4<100000000>, C4<0>, C4<0>, C4<0>; +v0x55e26af07550_0 .net/2u *"_ivl_0", 8 0, L_0x7fc8cdbe6018; 1 drivers +v0x55e26af0a360_0 .net *"_ivl_16", 32 0, L_0x55e26af67620; 1 drivers +v0x55e26af0a400_0 .net *"_ivl_18", 9 0, L_0x55e26af67700; 1 drivers +L_0x7fc8cdbe60a8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x55e26af0aa00_0 .net *"_ivl_21", 1 0, L_0x7fc8cdbe60a8; 1 drivers +v0x55e26af0aaa0_0 .net *"_ivl_24", 32 0, L_0x55e26af67980; 1 drivers +v0x55e26af0d5f0_0 .net *"_ivl_26", 9 0, L_0x55e26af67a50; 1 drivers +L_0x7fc8cdbe60f0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x55e26af0d690_0 .net *"_ivl_29", 1 0, L_0x7fc8cdbe60f0; 1 drivers +v0x55e26af54650_0 .net *"_ivl_35", 4 0, L_0x55e26af67ce0; 1 drivers +L_0x7fc8cdbe6138 .functor BUFT 1, C4<00001>, C4<0>, C4<0>, C4<0>; +v0x55e26af54730_0 .net/2u *"_ivl_36", 4 0, L_0x7fc8cdbe6138; 1 drivers +L_0x7fc8cdbe6060 .functor BUFT 1, C4<000000000>, C4<0>, C4<0>, C4<0>; +v0x55e26af54810_0 .net/2u *"_ivl_4", 8 0, L_0x7fc8cdbe6060; 1 drivers +L_0x7fc8cdbe6180 .functor BUFT 1, C4<0001>, C4<0>, C4<0>, C4<0>; +v0x55e26af548f0_0 .net/2u *"_ivl_40", 3 0, L_0x7fc8cdbe6180; 1 drivers +v0x55e26af549d0_0 .net *"_ivl_42", 0 0, L_0x55e26af68010; 1 drivers +v0x55e26af54a90_0 .net *"_ivl_45", 0 0, L_0x55e26af67de0; 1 drivers +L_0x7fc8cdbe61c8 .functor BUFT 1, C4<0010>, C4<0>, C4<0>, C4<0>; +v0x55e26af54b50_0 .net/2u *"_ivl_46", 3 0, L_0x7fc8cdbe61c8; 1 drivers +v0x55e26af54c30_0 .net *"_ivl_48", 0 0, L_0x55e26af68250; 1 drivers +v0x55e26af54cf0_0 .net *"_ivl_51", 0 0, L_0x55e26af0a8e0; 1 drivers +v0x55e26af54db0_0 .net *"_ivl_53", 0 0, L_0x55e26af0d490; 1 drivers +L_0x7fc8cdbe6210 .functor BUFT 1, C4<0100>, C4<0>, C4<0>, C4<0>; +v0x55e26af54f80_0 .net/2u *"_ivl_54", 3 0, L_0x7fc8cdbe6210; 1 drivers +v0x55e26af55060_0 .net *"_ivl_56", 0 0, L_0x55e26af684b0; 1 drivers +v0x55e26af55120_0 .net *"_ivl_59", 0 0, L_0x55e26af68630; 1 drivers +v0x55e26af551e0_0 .net *"_ivl_9", 0 0, L_0x55e26af67320; 1 drivers +v0x55e26af552a0_0 .var "fifo_count", 8 0; +v0x55e26af55380_0 .net "fifo_data", 31 0, L_0x55e26af67840; 1 drivers +v0x55e26af55460_0 .net "fifo_empty", 0 0, L_0x55e26af671e0; 1 drivers +v0x55e26af55520_0 .net "fifo_full", 0 0, L_0x55e26af67140; 1 drivers +v0x55e26af555e0_0 .net "fifo_last", 0 0, L_0x55e26af67bf0; 1 drivers +v0x55e26af556a0 .array "fifo_mem", 255 0, 32 0; +v0x55e26af55760_0 .net "fifo_rd_en", 0 0, L_0x55e26af68730; 1 drivers +v0x55e26af55820_0 .var "fifo_rd_ptr", 7 0; +v0x55e26af55900_0 .net "fifo_valid", 0 0, L_0x55e26af67530; 1 drivers +v0x55e26af559c0_0 .net "fifo_wr_en", 0 0, L_0x55e26af072e0; 1 drivers +v0x55e26af55a80_0 .var "fifo_wr_ptr", 7 0; +v0x55e26af55b60_0 .var/i "i", 31 0; +o0x7fc8cdc2f618 .functor BUFZ 1, C4; HiZ drive +v0x55e26af55e50_0 .net "i_clk", 0 0, o0x7fc8cdc2f618; 0 drivers +o0x7fc8cdc2f648 .functor BUFZ 32, C4; HiZ drive +v0x55e26af55f10_0 .net "i_data", 31 0, o0x7fc8cdc2f648; 0 drivers +o0x7fc8cdc2f678 .functor BUFZ 1, C4; HiZ drive +v0x55e26af55ff0_0 .net "i_last", 0 0, o0x7fc8cdc2f678; 0 drivers +o0x7fc8cdc2f6a8 .functor BUFZ 1, C4; HiZ drive +v0x55e26af560b0_0 .net "i_ready", 0 0, o0x7fc8cdc2f6a8; 0 drivers +o0x7fc8cdc2f6d8 .functor BUFZ 1, C4; HiZ drive +v0x55e26af56170_0 .net "i_rst_n", 0 0, o0x7fc8cdc2f6d8; 0 drivers +v0x55e26af56230_0 .net "i_valid", 0 0, o0x7fc8cdc2f708; 0 drivers +v0x55e26af562f0_0 .var "in_packetLost", 0 0; +v0x55e26af563b0_0 .var "in_state", 1 0; +v0x55e26af56490_0 .var "in_streamId", 15 0; +v0x55e26af56570_0 .var "msgLength", 15 0; +v0x55e26af56650_0 .var "next_state", 3 0; +v0x55e26af56730_0 .var "o_data", 295 0; +v0x55e26af56810_0 .net "o_packetLost", 0 0, L_0x55e26af0a240; 1 drivers +v0x55e26af568d0_0 .net "o_ready", 0 0, L_0x55e26af67460; 1 drivers +v0x55e26af56990_0 .var "o_valid", 0 0; +v0x55e26af56a50 .array "packetTracker", 0 31, 31 0; +v0x55e26af56b10_0 .var "seqNumber", 31 0; +v0x55e26af56bf0_0 .var "shiftReg", 295 0; +v0x55e26af56cd0_0 .var "state", 3 0; +v0x55e26af56db0_0 .var "streamId", 15 0; +v0x55e26af56e90_0 .net "stream_idx_w2", 4 0, L_0x55e26af67ed0; 1 drivers +E_0x55e26af1e610/0 .event negedge, v0x55e26af56170_0; +E_0x55e26af1e610/1 .event posedge, v0x55e26af55e50_0; +E_0x55e26af1e610 .event/or E_0x55e26af1e610/0, E_0x55e26af1e610/1; +E_0x55e26af1dbb0 .event anyedge, v0x55e26af56cd0_0, v0x55e26af55900_0, v0x55e26af555e0_0, v0x55e26af560b0_0; +L_0x55e26af67140 .cmp/eq 9, v0x55e26af552a0_0, L_0x7fc8cdbe6018; +L_0x55e26af671e0 .cmp/eq 9, v0x55e26af552a0_0, L_0x7fc8cdbe6060; +L_0x55e26af67320 .reduce/nor L_0x55e26af67140; +L_0x55e26af67460 .reduce/nor L_0x55e26af67140; +L_0x55e26af67530 .reduce/nor L_0x55e26af671e0; +L_0x55e26af67620 .array/port v0x55e26af556a0, L_0x55e26af67700; +L_0x55e26af67700 .concat [ 8 2 0 0], v0x55e26af55820_0, L_0x7fc8cdbe60a8; +L_0x55e26af67840 .part L_0x55e26af67620, 0, 32; +L_0x55e26af67980 .array/port v0x55e26af556a0, L_0x55e26af67a50; +L_0x55e26af67a50 .concat [ 8 2 0 0], v0x55e26af55820_0, L_0x7fc8cdbe60f0; +L_0x55e26af67bf0 .part L_0x55e26af67980, 32, 1; +L_0x55e26af67ce0 .part v0x55e26af56490_0, 0, 5; +L_0x55e26af67ed0 .arith/sub 5, L_0x55e26af67ce0, L_0x7fc8cdbe6138; +L_0x55e26af68010 .cmp/eq 4, v0x55e26af56cd0_0, L_0x7fc8cdbe6180; +L_0x55e26af68250 .cmp/eq 4, v0x55e26af56cd0_0, L_0x7fc8cdbe61c8; +L_0x55e26af684b0 .cmp/eq 4, v0x55e26af56cd0_0, L_0x7fc8cdbe6210; + .scope S_0x55e26aed5650; +T_0 ; + %wait E_0x55e26af1e610; + %load/vec4 v0x55e26af56170_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_0.0, 8; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55e26af55a80_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55e26af55820_0, 0; + %pushi/vec4 0, 0, 9; + %assign/vec4 v0x55e26af552a0_0, 0; + %jmp T_0.1; +T_0.0 ; + %load/vec4 v0x55e26af559c0_0; + %load/vec4 v0x55e26af55760_0; + %concat/vec4; draw_concat_vec4 + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_0.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_0.3, 6; + %load/vec4 v0x55e26af552a0_0; + %assign/vec4 v0x55e26af552a0_0, 0; + %jmp T_0.5; +T_0.2 ; + %load/vec4 v0x55e26af552a0_0; + %addi 1, 0, 9; + %assign/vec4 v0x55e26af552a0_0, 0; + %jmp T_0.5; +T_0.3 ; + %load/vec4 v0x55e26af552a0_0; + %subi 1, 0, 9; + %assign/vec4 v0x55e26af552a0_0, 0; + %jmp T_0.5; +T_0.5 ; + %pop/vec4 1; + %load/vec4 v0x55e26af559c0_0; + %flag_set/vec4 8; + %jmp/0xz T_0.6, 8; + %load/vec4 v0x55e26af55ff0_0; + %load/vec4 v0x55e26af55f10_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55e26af55a80_0; + %pad/u 10; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55e26af556a0, 0, 4; + %load/vec4 v0x55e26af55a80_0; + %addi 1, 0, 8; + %assign/vec4 v0x55e26af55a80_0, 0; +T_0.6 ; + %load/vec4 v0x55e26af55760_0; + %flag_set/vec4 8; + %jmp/0xz T_0.8, 8; + %load/vec4 v0x55e26af55820_0; + %addi 1, 0, 8; + %assign/vec4 v0x55e26af55820_0, 0; +T_0.8 ; +T_0.1 ; + %jmp T_0; + .thread T_0; + .scope S_0x55e26aed5650; +T_1 ; + %wait E_0x55e26af1e610; + %load/vec4 v0x55e26af56170_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55e26af563b0_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55e26af56490_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55e26af562f0_0, 0; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x55e26af55b60_0, 0, 32; +T_1.2 ; + %load/vec4 v0x55e26af55b60_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_1.3, 5; + %pushi/vec4 0, 0, 32; + %ix/getv/s 3, v0x55e26af55b60_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55e26af56a50, 0, 4; + %load/vec4 v0x55e26af55b60_0; + %addi 1, 0, 32; + %store/vec4 v0x55e26af55b60_0, 0, 32; + %jmp T_1.2; +T_1.3 ; + %jmp T_1.1; +T_1.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55e26af562f0_0, 0; + %load/vec4 v0x55e26af559c0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.4, 8; + %load/vec4 v0x55e26af563b0_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_1.6, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_1.7, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_1.8, 6; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55e26af563b0_0, 0; + %jmp T_1.10; +T_1.6 ; + %load/vec4 v0x55e26af55f10_0; + %parti/s 8, 0, 2; + %load/vec4 v0x55e26af55f10_0; + %parti/s 8, 8, 5; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55e26af56490_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55e26af563b0_0, 0; + %jmp T_1.10; +T_1.7 ; + %load/vec4 v0x55e26af56e90_0; + %pad/u 7; + %ix/vec4 4; + %load/vec4a v0x55e26af56a50, 4; + %addi 1, 0, 32; + %load/vec4 v0x55e26af56e90_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55e26af56a50, 0, 4; + %load/vec4 v0x55e26af56e90_0; + %pad/u 7; + %ix/vec4 4; + %load/vec4a v0x55e26af56a50, 4; + %addi 1, 0, 32; + %load/vec4 v0x55e26af55f10_0; + %parti/s 8, 0, 2; + %load/vec4 v0x55e26af55f10_0; + %parti/s 8, 8, 5; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55e26af55f10_0; + %parti/s 8, 16, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55e26af55f10_0; + %parti/s 8, 24, 6; + %concat/vec4; draw_concat_vec4 + %cmp/ne; + %jmp/0xz T_1.11, 4; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55e26af562f0_0, 0; +T_1.11 ; + %load/vec4 v0x55e26af55ff0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.13, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55e26af563b0_0, 0; + %jmp T_1.14; +T_1.13 ; + %pushi/vec4 2, 0, 2; + %assign/vec4 v0x55e26af563b0_0, 0; +T_1.14 ; + %jmp T_1.10; +T_1.8 ; + %load/vec4 v0x55e26af55ff0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.15, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55e26af563b0_0, 0; +T_1.15 ; + %jmp T_1.10; +T_1.10 ; + %pop/vec4 1; +T_1.4 ; +T_1.1 ; + %jmp T_1; + .thread T_1; + .scope S_0x55e26aed5650; +T_2 ; + %wait E_0x55e26af1e610; + %load/vec4 v0x55e26af56170_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55e26af56cd0_0, 0; + %jmp T_2.1; +T_2.0 ; + %load/vec4 v0x55e26af56650_0; + %assign/vec4 v0x55e26af56cd0_0, 0; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_0x55e26aed5650; +T_3 ; + %wait E_0x55e26af1dbb0; + %load/vec4 v0x55e26af56cd0_0; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_3.0, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_3.1, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_3.2, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_3.3, 6; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x55e26af56650_0, 0, 4; + %jmp T_3.5; +T_3.0 ; + %load/vec4 v0x55e26af55900_0; + %flag_set/vec4 8; + %jmp/0xz T_3.6, 8; + %pushi/vec4 2, 0, 4; + %store/vec4 v0x55e26af56650_0, 0, 4; + %jmp T_3.7; +T_3.6 ; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x55e26af56650_0, 0, 4; +T_3.7 ; + %jmp T_3.5; +T_3.1 ; + %load/vec4 v0x55e26af55900_0; + %flag_set/vec4 8; + %jmp/0xz T_3.8, 8; + %pushi/vec4 4, 0, 4; + %store/vec4 v0x55e26af56650_0, 0, 4; + %jmp T_3.9; +T_3.8 ; + %pushi/vec4 2, 0, 4; + %store/vec4 v0x55e26af56650_0, 0, 4; +T_3.9 ; + %jmp T_3.5; +T_3.2 ; + %load/vec4 v0x55e26af55900_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_3.12, 9; + %load/vec4 v0x55e26af555e0_0; + %and; +T_3.12; + %flag_set/vec4 8; + %jmp/0xz T_3.10, 8; + %pushi/vec4 8, 0, 4; + %store/vec4 v0x55e26af56650_0, 0, 4; + %jmp T_3.11; +T_3.10 ; + %pushi/vec4 4, 0, 4; + %store/vec4 v0x55e26af56650_0, 0, 4; +T_3.11 ; + %jmp T_3.5; +T_3.3 ; + %load/vec4 v0x55e26af560b0_0; + %flag_set/vec4 8; + %jmp/0xz T_3.13, 8; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x55e26af56650_0, 0, 4; + %jmp T_3.14; +T_3.13 ; + %pushi/vec4 8, 0, 4; + %store/vec4 v0x55e26af56650_0, 0, 4; +T_3.14 ; + %jmp T_3.5; +T_3.5 ; + %pop/vec4 1; + %jmp T_3; + .thread T_3, $push; + .scope S_0x55e26aed5650; +T_4 ; + %wait E_0x55e26af1e610; + %load/vec4 v0x55e26af56170_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55e26af56990_0, 0; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v0x55e26af56cd0_0; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_4.2, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_4.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_4.4, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_4.5, 6; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55e26af56990_0, 0; + %jmp T_4.7; +T_4.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55e26af56990_0, 0; + %jmp T_4.7; +T_4.3 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55e26af56990_0, 0; + %jmp T_4.7; +T_4.4 ; + %load/vec4 v0x55e26af55900_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_4.10, 9; + %load/vec4 v0x55e26af555e0_0; + %and; +T_4.10; + %flag_set/vec4 8; + %jmp/0xz T_4.8, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55e26af56990_0, 0; + %jmp T_4.9; +T_4.8 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55e26af56990_0, 0; +T_4.9 ; + %jmp T_4.7; +T_4.5 ; + %load/vec4 v0x55e26af560b0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.11, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55e26af56990_0, 0; + %jmp T_4.12; +T_4.11 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55e26af56990_0, 0; +T_4.12 ; + %jmp T_4.7; +T_4.7 ; + %pop/vec4 1; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0x55e26aed5650; +T_5 ; + %wait E_0x55e26af1e610; + %load/vec4 v0x55e26af56170_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %pushi/vec4 0, 0, 296; + %assign/vec4 v0x55e26af56730_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55e26af56570_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55e26af56db0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55e26af56b10_0, 0; + %pushi/vec4 0, 0, 296; + %assign/vec4 v0x55e26af56bf0_0, 0; + %jmp T_5.1; +T_5.0 ; + %load/vec4 v0x55e26af56cd0_0; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_5.2, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_5.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_5.4, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_5.5, 6; + %pushi/vec4 0, 0, 296; + %assign/vec4 v0x55e26af56730_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55e26af56570_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55e26af56db0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55e26af56b10_0, 0; + %pushi/vec4 0, 0, 296; + %assign/vec4 v0x55e26af56bf0_0, 0; + %jmp T_5.7; +T_5.2 ; + %pushi/vec4 0, 0, 296; + %assign/vec4 v0x55e26af56bf0_0, 0; + %load/vec4 v0x55e26af55900_0; + %flag_set/vec4 8; + %jmp/0xz T_5.8, 8; + %load/vec4 v0x55e26af55380_0; + %parti/s 8, 16, 6; + %load/vec4 v0x55e26af55380_0; + %parti/s 8, 24, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55e26af56570_0, 0; + %load/vec4 v0x55e26af55380_0; + %parti/s 8, 0, 2; + %load/vec4 v0x55e26af55380_0; + %parti/s 8, 8, 5; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55e26af56db0_0, 0; + %jmp T_5.9; +T_5.8 ; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55e26af56570_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55e26af56db0_0, 0; +T_5.9 ; + %jmp T_5.7; +T_5.3 ; + %load/vec4 v0x55e26af55900_0; + %flag_set/vec4 8; + %jmp/0xz T_5.10, 8; + %load/vec4 v0x55e26af55380_0; + %parti/s 8, 0, 2; + %load/vec4 v0x55e26af55380_0; + %parti/s 8, 8, 5; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55e26af55380_0; + %parti/s 8, 16, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55e26af55380_0; + %parti/s 8, 24, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55e26af56b10_0, 0; +T_5.10 ; + %jmp T_5.7; +T_5.4 ; + %load/vec4 v0x55e26af55900_0; + %flag_set/vec4 8; + %jmp/0xz T_5.12, 8; + %load/vec4 v0x55e26af56bf0_0; + %parti/s 264, 0, 2; + %load/vec4 v0x55e26af55380_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55e26af56bf0_0, 0; +T_5.12 ; + %jmp T_5.7; +T_5.5 ; + %load/vec4 v0x55e26af560b0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.14, 8; + %load/vec4 v0x55e26af56bf0_0; + %assign/vec4 v0x55e26af56730_0, 0; + %jmp T_5.15; +T_5.14 ; + %load/vec4 v0x55e26af56730_0; + %assign/vec4 v0x55e26af56730_0, 0; +T_5.15 ; + %jmp T_5.7; +T_5.7 ; + %pop/vec4 1; +T_5.1 ; + %jmp T_5; + .thread T_5; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "-"; + "/app/packet_handler.v"; diff --git a/sim_test b/sim_test new file mode 100755 index 0000000..3a7f421 --- /dev/null +++ b/sim_test @@ -0,0 +1,599 @@ +#! /usr/bin/vvp +:ivl_version "12.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +S_0x55c34e83f4c0 .scope module, "packet_handler" "packet_handler" 2 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "i_clk"; + .port_info 1 /INPUT 1 "i_rst_n"; + .port_info 2 /INPUT 32 "i_data"; + .port_info 3 /INPUT 1 "i_valid"; + .port_info 4 /INPUT 1 "i_last"; + .port_info 5 /INPUT 1 "i_ready"; + .port_info 6 /OUTPUT 296 "o_data"; + .port_info 7 /OUTPUT 1 "o_ready"; + .port_info 8 /OUTPUT 1 "o_valid"; + .port_info 9 /OUTPUT 1 "o_packetLost"; +P_0x55c34e83f650 .param/l "DATA" 1 2 121, C4<0100>; +P_0x55c34e83f690 .param/l "DONE" 1 2 122, C4<1000>; +P_0x55c34e83f6d0 .param/l "HEADER" 1 2 120, C4<0010>; +P_0x55c34e83f710 .param/l "IDLE" 1 2 119, C4<0001>; +P_0x55c34e83f750 .param/l "IN_DATA" 1 2 64, C4<10>; +P_0x55c34e83f790 .param/l "IN_W1" 1 2 62, C4<00>; +P_0x55c34e83f7d0 .param/l "IN_W2" 1 2 63, C4<01>; +o0x7f3acc1aa6a8 .functor BUFZ 1, C4; HiZ drive +L_0x55c34e86fbd0 .functor AND 1, o0x7f3acc1aa6a8, L_0x55c34e8cf830, C4<1>, C4<1>; +L_0x55c34e872e60 .functor BUFZ 1, v0x55c34e8be8e0_0, C4<0>, C4<0>, C4<0>; +L_0x55c34e873500 .functor AND 1, L_0x55c34e8d0270, L_0x55c34e8cfa40, C4<1>, C4<1>; +L_0x55c34e8760b0 .functor AND 1, L_0x55c34e8d04a0, L_0x55c34e8cfa40, C4<1>, C4<1>; +L_0x55c34e8d0660 .functor OR 1, L_0x55c34e873500, L_0x55c34e8760b0, C4<0>, C4<0>; +L_0x55c34e8d0390 .functor AND 1, L_0x55c34e8d0770, L_0x55c34e8cfa40, C4<1>, C4<1>; +L_0x55c34e8d0970 .functor OR 1, L_0x55c34e8d0660, L_0x55c34e8d0390, C4<0>, C4<0>; +L_0x7f3acc161018 .functor BUFT 1, C4<100000000>, C4<0>, C4<0>, C4<0>; +v0x55c34e86fe40_0 .net/2u *"_ivl_0", 8 0, L_0x7f3acc161018; 1 drivers +v0x55c34e872f80_0 .net *"_ivl_16", 32 0, L_0x55c34e8cfb30; 1 drivers +v0x55c34e873020_0 .net *"_ivl_18", 9 0, L_0x55c34e8cfc10; 1 drivers +L_0x7f3acc1610a8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x55c34e873620_0 .net *"_ivl_21", 1 0, L_0x7f3acc1610a8; 1 drivers +v0x55c34e8736c0_0 .net *"_ivl_24", 32 0, L_0x55c34e8cfe90; 1 drivers +v0x55c34e876210_0 .net *"_ivl_26", 9 0, L_0x55c34e8cff60; 1 drivers +L_0x7f3acc1610f0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x55c34e8762b0_0 .net *"_ivl_29", 1 0, L_0x7f3acc1610f0; 1 drivers +L_0x7f3acc161138 .functor BUFT 1, C4<0001>, C4<0>, C4<0>, C4<0>; +v0x55c34e8bce00_0 .net/2u *"_ivl_34", 3 0, L_0x7f3acc161138; 1 drivers +v0x55c34e8bcee0_0 .net *"_ivl_36", 0 0, L_0x55c34e8d0270; 1 drivers +v0x55c34e8bcfa0_0 .net *"_ivl_39", 0 0, L_0x55c34e873500; 1 drivers +L_0x7f3acc161060 .functor BUFT 1, C4<000000000>, C4<0>, C4<0>, C4<0>; +v0x55c34e8bd060_0 .net/2u *"_ivl_4", 8 0, L_0x7f3acc161060; 1 drivers +L_0x7f3acc161180 .functor BUFT 1, C4<0010>, C4<0>, C4<0>, C4<0>; +v0x55c34e8bd140_0 .net/2u *"_ivl_40", 3 0, L_0x7f3acc161180; 1 drivers +v0x55c34e8bd220_0 .net *"_ivl_42", 0 0, L_0x55c34e8d04a0; 1 drivers +v0x55c34e8bd2e0_0 .net *"_ivl_45", 0 0, L_0x55c34e8760b0; 1 drivers +v0x55c34e8bd3a0_0 .net *"_ivl_47", 0 0, L_0x55c34e8d0660; 1 drivers +L_0x7f3acc1611c8 .functor BUFT 1, C4<0100>, C4<0>, C4<0>, C4<0>; +v0x55c34e8bd460_0 .net/2u *"_ivl_48", 3 0, L_0x7f3acc1611c8; 1 drivers +v0x55c34e8bd540_0 .net *"_ivl_50", 0 0, L_0x55c34e8d0770; 1 drivers +v0x55c34e8bd710_0 .net *"_ivl_53", 0 0, L_0x55c34e8d0390; 1 drivers +v0x55c34e8bd7d0_0 .net *"_ivl_9", 0 0, L_0x55c34e8cf830; 1 drivers +v0x55c34e8bd890_0 .var "fifo_count", 8 0; +v0x55c34e8bd970_0 .net "fifo_data", 31 0, L_0x55c34e8cfd50; 1 drivers +v0x55c34e8bda50_0 .net "fifo_empty", 0 0, L_0x55c34e8cf6f0; 1 drivers +v0x55c34e8bdb10_0 .net "fifo_full", 0 0, L_0x55c34e8cf650; 1 drivers +v0x55c34e8bdbd0_0 .net "fifo_last", 0 0, L_0x55c34e8d0100; 1 drivers +v0x55c34e8bdc90 .array "fifo_mem", 255 0, 32 0; +v0x55c34e8bdd50_0 .net "fifo_rd_en", 0 0, L_0x55c34e8d0970; 1 drivers +v0x55c34e8bde10_0 .var "fifo_rd_ptr", 7 0; +v0x55c34e8bdef0_0 .net "fifo_valid", 0 0, L_0x55c34e8cfa40; 1 drivers +v0x55c34e8bdfb0_0 .net "fifo_wr_en", 0 0, L_0x55c34e86fbd0; 1 drivers +v0x55c34e8be070_0 .var "fifo_wr_ptr", 7 0; +v0x55c34e8be150_0 .var/i "i", 31 0; +o0x7f3acc1aa5b8 .functor BUFZ 1, C4; HiZ drive +v0x55c34e8be230_0 .net "i_clk", 0 0, o0x7f3acc1aa5b8; 0 drivers +o0x7f3acc1aa5e8 .functor BUFZ 32, C4; HiZ drive +v0x55c34e8be2f0_0 .net "i_data", 31 0, o0x7f3acc1aa5e8; 0 drivers +o0x7f3acc1aa618 .functor BUFZ 1, C4; HiZ drive +v0x55c34e8be5e0_0 .net "i_last", 0 0, o0x7f3acc1aa618; 0 drivers +o0x7f3acc1aa648 .functor BUFZ 1, C4; HiZ drive +v0x55c34e8be6a0_0 .net "i_ready", 0 0, o0x7f3acc1aa648; 0 drivers +o0x7f3acc1aa678 .functor BUFZ 1, C4; HiZ drive +v0x55c34e8be760_0 .net "i_rst_n", 0 0, o0x7f3acc1aa678; 0 drivers +v0x55c34e8be820_0 .net "i_valid", 0 0, o0x7f3acc1aa6a8; 0 drivers +v0x55c34e8be8e0_0 .var "in_packetLost", 0 0; +v0x55c34e8be9a0_0 .var "in_state", 1 0; +v0x55c34e8bea80_0 .var "in_streamId", 15 0; +v0x55c34e8beb60_0 .var "msgLength", 15 0; +v0x55c34e8bec40_0 .var "next_state", 3 0; +v0x55c34e8bed20_0 .var "o_data", 295 0; +v0x55c34e8bee00_0 .net "o_packetLost", 0 0, L_0x55c34e872e60; 1 drivers +v0x55c34e8beec0_0 .net "o_ready", 0 0, L_0x55c34e8cf970; 1 drivers +v0x55c34e8bef80_0 .var "o_valid", 0 0; +v0x55c34e8bf040 .array "packetTracker", 0 31, 31 0; +v0x55c34e8bf100_0 .var "seqNumber", 31 0; +v0x55c34e8bf1e0_0 .var "shiftReg", 295 0; +v0x55c34e8bf2c0_0 .var "state", 3 0; +v0x55c34e8bf3a0_0 .var "streamId", 15 0; +E_0x55c34e887810/0 .event negedge, v0x55c34e8be760_0; +E_0x55c34e887810/1 .event posedge, v0x55c34e8be230_0; +E_0x55c34e887810 .event/or E_0x55c34e887810/0, E_0x55c34e887810/1; +E_0x55c34e887b80 .event anyedge, v0x55c34e8bf2c0_0, v0x55c34e8bdef0_0, v0x55c34e8bdbd0_0, v0x55c34e8be6a0_0; +L_0x55c34e8cf650 .cmp/eq 9, v0x55c34e8bd890_0, L_0x7f3acc161018; +L_0x55c34e8cf6f0 .cmp/eq 9, v0x55c34e8bd890_0, L_0x7f3acc161060; +L_0x55c34e8cf830 .reduce/nor L_0x55c34e8cf650; +L_0x55c34e8cf970 .reduce/nor L_0x55c34e8cf650; +L_0x55c34e8cfa40 .reduce/nor L_0x55c34e8cf6f0; +L_0x55c34e8cfb30 .array/port v0x55c34e8bdc90, L_0x55c34e8cfc10; +L_0x55c34e8cfc10 .concat [ 8 2 0 0], v0x55c34e8bde10_0, L_0x7f3acc1610a8; +L_0x55c34e8cfd50 .part L_0x55c34e8cfb30, 0, 32; +L_0x55c34e8cfe90 .array/port v0x55c34e8bdc90, L_0x55c34e8cff60; +L_0x55c34e8cff60 .concat [ 8 2 0 0], v0x55c34e8bde10_0, L_0x7f3acc1610f0; +L_0x55c34e8d0100 .part L_0x55c34e8cfe90, 32, 1; +L_0x55c34e8d0270 .cmp/eq 4, v0x55c34e8bf2c0_0, L_0x7f3acc161138; +L_0x55c34e8d04a0 .cmp/eq 4, v0x55c34e8bf2c0_0, L_0x7f3acc161180; +L_0x55c34e8d0770 .cmp/eq 4, v0x55c34e8bf2c0_0, L_0x7f3acc1611c8; + .scope S_0x55c34e83f4c0; +T_0 ; + %wait E_0x55c34e887810; + %load/vec4 v0x55c34e8be760_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_0.0, 8; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55c34e8be070_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55c34e8bde10_0, 0; + %pushi/vec4 0, 0, 9; + %assign/vec4 v0x55c34e8bd890_0, 0; + %jmp T_0.1; +T_0.0 ; + %load/vec4 v0x55c34e8bdfb0_0; + %load/vec4 v0x55c34e8bdd50_0; + %concat/vec4; draw_concat_vec4 + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_0.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_0.3, 6; + %load/vec4 v0x55c34e8bd890_0; + %assign/vec4 v0x55c34e8bd890_0, 0; + %jmp T_0.5; +T_0.2 ; + %load/vec4 v0x55c34e8bd890_0; + %addi 1, 0, 9; + %assign/vec4 v0x55c34e8bd890_0, 0; + %jmp T_0.5; +T_0.3 ; + %load/vec4 v0x55c34e8bd890_0; + %subi 1, 0, 9; + %assign/vec4 v0x55c34e8bd890_0, 0; + %jmp T_0.5; +T_0.5 ; + %pop/vec4 1; + %load/vec4 v0x55c34e8bdfb0_0; + %flag_set/vec4 8; + %jmp/0xz T_0.6, 8; + %load/vec4 v0x55c34e8be5e0_0; + %load/vec4 v0x55c34e8be2f0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55c34e8be070_0; + %pad/u 10; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55c34e8bdc90, 0, 4; + %load/vec4 v0x55c34e8be070_0; + %addi 1, 0, 8; + %assign/vec4 v0x55c34e8be070_0, 0; +T_0.6 ; + %load/vec4 v0x55c34e8bdd50_0; + %flag_set/vec4 8; + %jmp/0xz T_0.8, 8; + %load/vec4 v0x55c34e8bde10_0; + %addi 1, 0, 8; + %assign/vec4 v0x55c34e8bde10_0, 0; +T_0.8 ; +T_0.1 ; + %jmp T_0; + .thread T_0; + .scope S_0x55c34e83f4c0; +T_1 ; + %wait E_0x55c34e887810; + %load/vec4 v0x55c34e8be760_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55c34e8be9a0_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55c34e8bea80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55c34e8be8e0_0, 0; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x55c34e8be150_0, 0, 32; +T_1.2 ; + %load/vec4 v0x55c34e8be150_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_1.3, 5; + %pushi/vec4 0, 0, 32; + %ix/getv/s 3, v0x55c34e8be150_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55c34e8bf040, 0, 4; + %load/vec4 v0x55c34e8be150_0; + %addi 1, 0, 32; + %store/vec4 v0x55c34e8be150_0, 0, 32; + %jmp T_1.2; +T_1.3 ; + %jmp T_1.1; +T_1.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55c34e8be8e0_0, 0; + %load/vec4 v0x55c34e8bdfb0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.4, 8; + %load/vec4 v0x55c34e8be9a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_1.6, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_1.7, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_1.8, 6; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55c34e8be9a0_0, 0; + %jmp T_1.10; +T_1.6 ; + %load/vec4 v0x55c34e8be2f0_0; + %parti/s 8, 0, 2; + %load/vec4 v0x55c34e8be2f0_0; + %parti/s 8, 8, 5; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55c34e8bea80_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55c34e8be9a0_0, 0; + %jmp T_1.10; +T_1.7 ; + %load/vec4 v0x55c34e8bea80_0; + %pad/u 32; + %subi 1, 0, 32; + %ix/vec4 4; + %load/vec4a v0x55c34e8bf040, 4; + %addi 1, 0, 32; + %load/vec4 v0x55c34e8bea80_0; + %pad/u 32; + %subi 1, 0, 32; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55c34e8bf040, 0, 4; + %load/vec4 v0x55c34e8bea80_0; + %pad/u 32; + %subi 1, 0, 32; + %ix/vec4 4; + %load/vec4a v0x55c34e8bf040, 4; + %addi 1, 0, 32; + %load/vec4 v0x55c34e8be2f0_0; + %parti/s 8, 0, 2; + %load/vec4 v0x55c34e8be2f0_0; + %parti/s 8, 8, 5; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55c34e8be2f0_0; + %parti/s 8, 16, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55c34e8be2f0_0; + %parti/s 8, 24, 6; + %concat/vec4; draw_concat_vec4 + %cmp/ne; + %jmp/0xz T_1.11, 4; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55c34e8be8e0_0, 0; +T_1.11 ; + %load/vec4 v0x55c34e8be5e0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.13, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55c34e8be9a0_0, 0; + %jmp T_1.14; +T_1.13 ; + %pushi/vec4 2, 0, 2; + %assign/vec4 v0x55c34e8be9a0_0, 0; +T_1.14 ; + %jmp T_1.10; +T_1.8 ; + %load/vec4 v0x55c34e8be5e0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.15, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55c34e8be9a0_0, 0; +T_1.15 ; + %jmp T_1.10; +T_1.10 ; + %pop/vec4 1; +T_1.4 ; +T_1.1 ; + %jmp T_1; + .thread T_1; + .scope S_0x55c34e83f4c0; +T_2 ; + %wait E_0x55c34e887810; + %load/vec4 v0x55c34e8be760_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55c34e8bf2c0_0, 0; + %jmp T_2.1; +T_2.0 ; + %load/vec4 v0x55c34e8bec40_0; + %assign/vec4 v0x55c34e8bf2c0_0, 0; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_0x55c34e83f4c0; +T_3 ; + %wait E_0x55c34e887b80; + %load/vec4 v0x55c34e8bf2c0_0; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_3.0, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_3.1, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_3.2, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_3.3, 6; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x55c34e8bec40_0, 0, 4; + %jmp T_3.5; +T_3.0 ; + %load/vec4 v0x55c34e8bdef0_0; + %flag_set/vec4 8; + %jmp/0xz T_3.6, 8; + %pushi/vec4 2, 0, 4; + %store/vec4 v0x55c34e8bec40_0, 0, 4; + %jmp T_3.7; +T_3.6 ; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x55c34e8bec40_0, 0, 4; +T_3.7 ; + %jmp T_3.5; +T_3.1 ; + %load/vec4 v0x55c34e8bdef0_0; + %flag_set/vec4 8; + %jmp/0xz T_3.8, 8; + %pushi/vec4 4, 0, 4; + %store/vec4 v0x55c34e8bec40_0, 0, 4; + %jmp T_3.9; +T_3.8 ; + %pushi/vec4 2, 0, 4; + %store/vec4 v0x55c34e8bec40_0, 0, 4; +T_3.9 ; + %jmp T_3.5; +T_3.2 ; + %load/vec4 v0x55c34e8bdef0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_3.12, 9; + %load/vec4 v0x55c34e8bdbd0_0; + %and; +T_3.12; + %flag_set/vec4 8; + %jmp/0xz T_3.10, 8; + %pushi/vec4 8, 0, 4; + %store/vec4 v0x55c34e8bec40_0, 0, 4; + %jmp T_3.11; +T_3.10 ; + %pushi/vec4 4, 0, 4; + %store/vec4 v0x55c34e8bec40_0, 0, 4; +T_3.11 ; + %jmp T_3.5; +T_3.3 ; + %load/vec4 v0x55c34e8be6a0_0; + %flag_set/vec4 8; + %jmp/0xz T_3.13, 8; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x55c34e8bec40_0, 0, 4; + %jmp T_3.14; +T_3.13 ; + %pushi/vec4 8, 0, 4; + %store/vec4 v0x55c34e8bec40_0, 0, 4; +T_3.14 ; + %jmp T_3.5; +T_3.5 ; + %pop/vec4 1; + %jmp T_3; + .thread T_3, $push; + .scope S_0x55c34e83f4c0; +T_4 ; + %wait E_0x55c34e887810; + %load/vec4 v0x55c34e8be760_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55c34e8bef80_0, 0; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v0x55c34e8bf2c0_0; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_4.2, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_4.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_4.4, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_4.5, 6; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55c34e8bef80_0, 0; + %jmp T_4.7; +T_4.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55c34e8bef80_0, 0; + %jmp T_4.7; +T_4.3 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55c34e8bef80_0, 0; + %jmp T_4.7; +T_4.4 ; + %load/vec4 v0x55c34e8bdef0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_4.10, 9; + %load/vec4 v0x55c34e8bdbd0_0; + %and; +T_4.10; + %flag_set/vec4 8; + %jmp/0xz T_4.8, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55c34e8bef80_0, 0; + %jmp T_4.9; +T_4.8 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55c34e8bef80_0, 0; +T_4.9 ; + %jmp T_4.7; +T_4.5 ; + %load/vec4 v0x55c34e8be6a0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.11, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55c34e8bef80_0, 0; + %jmp T_4.12; +T_4.11 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55c34e8bef80_0, 0; +T_4.12 ; + %jmp T_4.7; +T_4.7 ; + %pop/vec4 1; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0x55c34e83f4c0; +T_5 ; + %wait E_0x55c34e887810; + %load/vec4 v0x55c34e8be760_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %pushi/vec4 0, 0, 296; + %assign/vec4 v0x55c34e8bed20_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55c34e8beb60_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55c34e8bf3a0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55c34e8bf100_0, 0; + %pushi/vec4 0, 0, 296; + %assign/vec4 v0x55c34e8bf1e0_0, 0; + %jmp T_5.1; +T_5.0 ; + %load/vec4 v0x55c34e8bf2c0_0; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_5.2, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_5.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_5.4, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_5.5, 6; + %pushi/vec4 0, 0, 296; + %assign/vec4 v0x55c34e8bed20_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55c34e8beb60_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55c34e8bf3a0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55c34e8bf100_0, 0; + %pushi/vec4 0, 0, 296; + %assign/vec4 v0x55c34e8bf1e0_0, 0; + %jmp T_5.7; +T_5.2 ; + %pushi/vec4 0, 0, 296; + %assign/vec4 v0x55c34e8bf1e0_0, 0; + %load/vec4 v0x55c34e8bdef0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.8, 8; + %load/vec4 v0x55c34e8bd970_0; + %parti/s 8, 16, 6; + %load/vec4 v0x55c34e8bd970_0; + %parti/s 8, 24, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55c34e8beb60_0, 0; + %load/vec4 v0x55c34e8bd970_0; + %parti/s 8, 0, 2; + %load/vec4 v0x55c34e8bd970_0; + %parti/s 8, 8, 5; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55c34e8bf3a0_0, 0; + %jmp T_5.9; +T_5.8 ; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55c34e8beb60_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x55c34e8bf3a0_0, 0; +T_5.9 ; + %jmp T_5.7; +T_5.3 ; + %load/vec4 v0x55c34e8bdef0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.10, 8; + %load/vec4 v0x55c34e8bd970_0; + %parti/s 8, 0, 2; + %load/vec4 v0x55c34e8bd970_0; + %parti/s 8, 8, 5; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55c34e8bd970_0; + %parti/s 8, 16, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55c34e8bd970_0; + %parti/s 8, 24, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55c34e8bf100_0, 0; +T_5.10 ; + %jmp T_5.7; +T_5.4 ; + %load/vec4 v0x55c34e8bdef0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.12, 8; + %load/vec4 v0x55c34e8bf1e0_0; + %parti/s 264, 0, 2; + %load/vec4 v0x55c34e8bd970_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55c34e8bf1e0_0, 0; +T_5.12 ; + %jmp T_5.7; +T_5.5 ; + %load/vec4 v0x55c34e8be6a0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.14, 8; + %load/vec4 v0x55c34e8bf1e0_0; + %assign/vec4 v0x55c34e8bed20_0, 0; + %jmp T_5.15; +T_5.14 ; + %load/vec4 v0x55c34e8bed20_0; + %assign/vec4 v0x55c34e8bed20_0, 0; +T_5.15 ; + %jmp T_5.7; +T_5.7 ; + %pop/vec4 1; +T_5.1 ; + %jmp T_5; + .thread T_5; +# The file index is used to find the file name in the following table. +:file_names 3; + "N/A"; + ""; + "new_packet_handler.v";