fix(mir-lower): give an aggregate niche payload's leaves typed slots (#1591)

## What This PR Does

Decomposes struct/tuple enum payloads with a pointer niche
(`Option<RopePair>`, `Option<(f32, f32, &mut f32)>`, `Option<(usize,
&T)>`) into per-leaf typed slots in `mir-lower` (`build_enum_slot_map`),
keeping construction and payload extraction in SSA registers instead of
spilling through a `.local` stack depot.

---

### Why Pointer-Niche Struct/Tuple Payloads Spilled to `.local`

Previously, when a struct or tuple payload inside an `Option` had its
niche on a pointer field, `build_enum_slot_map` gave only the pointer a
typed slot in the enum's LLVM struct and represented all other fields as
`[N x i8]` or `i64` filler bytes. Reading or writing the payload then
went through an `alloca` stack slot with byte-slice stores and a wide
struct load, which LLVM's SROA pass could not promote back to registers.

```text
BEFORE (Option<(f32, f32, &mut f32)> with pointer niche at byte 8):
  LLVM enum struct: { i64_filler, ptr }
  construct / read: alloca + byte-slice stores + wide load ──► 16 B .local stack depot in PTX

AFTER (leaf-by-leaf typed slots when leaves are aligned and non-overlapping):
  LLVM enum struct: { f32, f32, ptr }
  construct / read: llvm.extractvalue + llvm.insertvalue   ──► pure SSA registers (0 B .local)
```

* Fails closed to the existing memory path if any leaf overlaps another
variant's differently typed claim, is unaligned (packed struct), or
contains `i1` (`bool`).

---

## Verification

* **GPU Execution (`RTX 5090`, `sm_120a`)**: `cargo oxide run
enum_niche_payload` and `--verify-ptx` pass with `0` `.local` bytes
across all entries (`compute-sanitizer --tool memcheck`: `0 errors`);
`set_discriminant_niche` also drops from `16 B` `.local` to `0 B`.
* **Tests & CI Gates**: `cargo test -p mir-lower --all-targets`
(`517/517 PASS`), `just fmt-check`, `cargo clippy`, and repository
guards all pass.

Closes #1590

Signed-off-by: midagedev <midagedev@gmail.com>
Signed-off-by: nihalpasham <nihalp@nvidia.com>
Co-authored-by: nihalpasham <nihalp@nvidia.com>

Author: midagedev