Describe the bug
We found further irregularities in the ADC, which follow a different pattern to the ones described in the original bug report. These outlier ADC values seem to only appear on one board, across all channels and scan modes (highrange, lowrange, preCC), though they are most apparent in highrange scans.
The irregularities appear as slightly lower/higher (on the rising and falling edge, respectively) than expected ADC values, resulting in apparent "gaps" in the scan. The issue does not seem specific to any phase or bunch-crossing.
We believe the issue is connected to some trigger or delay - following the red-tinted points on the figure above, we can trace a full scan shifted to the right.
To Reproduce
Steps to reproduce the behavior:
- Clone and compile
pflib
- Run
pftool with ~/pflib/build/pftool ~/pflib/config/pftool/fiberless-zcu.yaml
- Run
TASKS/LEVEL_PEDESTALS
- Run
TASKS/PARAMETER_TIMESCAN with the following settings:
- Events per time point: 100
- Use pre-CC charge injection: N
- Use highrange or lowrange: Y
- Scan TOT?: N
- Setting for calib pulse amplitude: 256
- Pulse into one channel or all channels: N
- Channel to pulse into: any
- Starting BX: -1
- Number of BX: 5
- Filename: ...
- File of parameter points: ...
Expected behavior
We expect a clean signal as seen in the following figure - no gaps or outlier ADC values.
Environment:
- ZCU: Lund
- pftoolrc being loaded: None
- Firmware version: hcal-zcu102-20250529-120007-10dbd92
- pflib version: v3.9.5 (and older)
Describe the bug
We found further irregularities in the ADC, which follow a different pattern to the ones described in the original bug report. These outlier ADC values seem to only appear on one board, across all channels and scan modes (highrange, lowrange, preCC), though they are most apparent in highrange scans.
The irregularities appear as slightly lower/higher (on the rising and falling edge, respectively) than expected ADC values, resulting in apparent "gaps" in the scan. The issue does not seem specific to any phase or bunch-crossing.
We believe the issue is connected to some trigger or delay - following the red-tinted points on the figure above, we can trace a full scan shifted to the right.
To Reproduce
Steps to reproduce the behavior:
pflibpftoolwith~/pflib/build/pftool ~/pflib/config/pftool/fiberless-zcu.yamlTASKS/LEVEL_PEDESTALSTASKS/PARAMETER_TIMESCANwith the following settings:Expected behavior
We expect a clean signal as seen in the following figure - no gaps or outlier ADC values.
Environment: