From e0c1cf1fcb550233a44df3dd0c422e815e770cb7 Mon Sep 17 00:00:00 2001 From: Abhinav Anil Sharma Date: Mon, 24 Feb 2025 19:33:40 -0500 Subject: [PATCH 1/3] i#7157 dyn inject: Add switch injection count to schedule_stats Adds the count of instances where the context switch sequence was injected to the schedule_stats tool output. Modifies the switch_insertion test to use schedule_stats instead of basic_counts. This helps reveal a bug in context switch trace template insertion that causes the injection to happen many more times than the context switch events. This diff is split out from #7299 which fixes the above bug. Issue: #7157 --- clients/drcachesim/common/memtrace_stream.h | 6 +++- .../drcachesim/scheduler/scheduler_impl.cpp | 2 ++ .../tests/switch_insertion.templatex | 32 +++++++++++++++---- clients/drcachesim/tools/schedule_stats.cpp | 7 +++- clients/drcachesim/tools/schedule_stats.h | 4 ++- suite/tests/CMakeLists.txt | 2 +- 6 files changed, 43 insertions(+), 10 deletions(-) diff --git a/clients/drcachesim/common/memtrace_stream.h b/clients/drcachesim/common/memtrace_stream.h index b479ff5785..44e48891e3 100644 --- a/clients/drcachesim/common/memtrace_stream.h +++ b/clients/drcachesim/common/memtrace_stream.h @@ -1,5 +1,5 @@ /* ********************************************************** - * Copyright (c) 2022-2024 Google, Inc. All rights reserved. + * Copyright (c) 2022-2025 Google, Inc. All rights reserved. * **********************************************************/ /* @@ -112,6 +112,10 @@ class memtrace_stream_t { * inputs from being scheduled onto an output. */ SCHED_STAT_HIT_OUTPUT_LIMIT, + /** + * Counts the instances when the context switch sequence was injected. + */ + SCHED_STAT_SWITCH_SEQUENCE_INJECTIONS, /** Count of statistic types. */ SCHED_STAT_TYPE_COUNT, }; diff --git a/clients/drcachesim/scheduler/scheduler_impl.cpp b/clients/drcachesim/scheduler/scheduler_impl.cpp index 3ff55edf36..1a14d7e364 100644 --- a/clients/drcachesim/scheduler/scheduler_impl.cpp +++ b/clients/drcachesim/scheduler/scheduler_impl.cpp @@ -2308,6 +2308,8 @@ scheduler_impl_tmpl_t::set_cur_input( // XXX: These will appear before the top headers of a new thread which is slightly // odd to have regular records with the new tid before the top headers. if (!switch_sequence_[switch_type].empty()) { + ++outputs_[output] + .stats[memtrace_stream_t::SCHED_STAT_SWITCH_SEQUENCE_INJECTIONS]; for (int i = static_cast(switch_sequence_[switch_type].size()) - 1; i >= 0; --i) { RecordType record = switch_sequence_[switch_type][i]; diff --git a/clients/drcachesim/tests/switch_insertion.templatex b/clients/drcachesim/tests/switch_insertion.templatex index 91f6dc0466..8fa7ecde01 100644 --- a/clients/drcachesim/tests/switch_insertion.templatex +++ b/clients/drcachesim/tests/switch_insertion.templatex @@ -1,8 +1,28 @@ -Basic counts tool results: +Schedule stats tool results: Total counts: - [1-9][0-9][0-9][0-9][0-9][0-9] total \(fetched\) instructions - 5971 total unique \(fetched\) instructions - [1-9][0-9][0-9][0-9][0-9][0-9] total userspace instructions - [1-9][0-9][0-9] total kernel instructions - [1-9][0-9][0-9][0-9][0-9][0-9] total non-fetched instructions + 4 cores +.* + 639664 instructions + 11 total context switches +.* + 6 voluntary context switches + 0 direct context switches + 363 context switch sequence injections +.* + 9 switches input-to-input + 5 switches input-to-idle + 2 switches idle-to-input +.* +Core #0 counts: +.* + 117223 instructions + 8 total context switches +.* + 3 voluntary context switches + 0 direct context switches + 104 context switch sequence injections +.* + 6 switches input-to-input + 3 switches input-to-idle + 2 switches idle-to-input .* diff --git a/clients/drcachesim/tools/schedule_stats.cpp b/clients/drcachesim/tools/schedule_stats.cpp index 5d4b26b6b8..abc1ae6e04 100644 --- a/clients/drcachesim/tools/schedule_stats.cpp +++ b/clients/drcachesim/tools/schedule_stats.cpp @@ -1,5 +1,5 @@ /* ********************************************************** - * Copyright (c) 2017-2024 Google, Inc. All rights reserved. + * Copyright (c) 2017-2025 Google, Inc. All rights reserved. * **********************************************************/ /* @@ -166,6 +166,9 @@ schedule_stats_t::get_scheduler_stats(memtrace_stream_t *stream, counters_t &cou memtrace_stream_t::SCHED_STAT_RUNQUEUE_REBALANCES)); counters.at_output_limit = static_cast( stream->get_schedule_statistic(memtrace_stream_t::SCHED_STAT_HIT_OUTPUT_LIMIT)); + counters.switch_sequence_injections = + static_cast(stream->get_schedule_statistic( + memtrace_stream_t::SCHED_STAT_SWITCH_SEQUENCE_INJECTIONS)); // XXX: Currently, schedule_stats is measuring swap-ins to a real input. If we // want to match what "perf" targeting this app would record, which is swap-outs, @@ -420,6 +423,8 @@ schedule_stats_t::print_counters(const counters_t &counters) << counters.voluntary_switches << " voluntary context switches\n"; std::cerr << std::setw(12) << counters.direct_switches << " direct context switches\n"; + std::cerr << std::setw(12) << counters.switch_sequence_injections + << " context switch sequence injections\n"; print_percentage(static_cast(counters.voluntary_switches), static_cast(counters.total_switches), "% voluntary switches\n"); diff --git a/clients/drcachesim/tools/schedule_stats.h b/clients/drcachesim/tools/schedule_stats.h index cc082a8423..95133455d4 100644 --- a/clients/drcachesim/tools/schedule_stats.h +++ b/clients/drcachesim/tools/schedule_stats.h @@ -1,5 +1,5 @@ /* ********************************************************** - * Copyright (c) 2023-2024 Google, Inc. All rights reserved. + * Copyright (c) 2023-2025 Google, Inc. All rights reserved. * **********************************************************/ /* @@ -216,6 +216,7 @@ class schedule_stats_t : public analysis_tool_t { syscalls += rhs.syscalls; maybe_blocking_syscalls += rhs.maybe_blocking_syscalls; direct_switch_requests += rhs.direct_switch_requests; + switch_sequence_injections += rhs.switch_sequence_injections; observed_migrations += rhs.observed_migrations; waits += rhs.waits; idles += rhs.idles; @@ -252,6 +253,7 @@ class schedule_stats_t : public analysis_tool_t { int64_t syscalls = 0; int64_t maybe_blocking_syscalls = 0; int64_t direct_switch_requests = 0; + int64_t switch_sequence_injections = 0; // Our observed migrations will be <= the scheduler's reported migrations // for a dynamic schedule as we don't know the initial runqueue allocation // and so can't see the migration of an input that didn't execute in the diff --git a/suite/tests/CMakeLists.txt b/suite/tests/CMakeLists.txt index aa1c39b6d2..9ec5d3d6f4 100644 --- a/suite/tests/CMakeLists.txt +++ b/suite/tests/CMakeLists.txt @@ -4067,7 +4067,7 @@ if (BUILD_CLIENTS) set(switch_file "${PROJECT_SOURCE_DIR}/clients/drcachesim/tests/mock_switch_sequences.x64.zip") torunonly_simtool(switch_insertion ${ci_shared_app} - "-indir ${thread_trace_dir} -tool basic_counts -core_sharded -sched_quantum 1000 -sched_switch_file ${switch_file}" + "-indir ${thread_trace_dir} -tool schedule_stats -core_sharded -sched_quantum 1000 -sched_switch_file ${switch_file}" "") set(tool.switch_insertion_rawtemp ON) # no preprocessor From 83e6a72f21a6a5a64ac5603d614dafef882d0213 Mon Sep 17 00:00:00 2001 From: Abhinav Anil Sharma Date: Mon, 24 Feb 2025 19:50:10 -0500 Subject: [PATCH 2/3] Update other test templates --- clients/drcachesim/tests/core_serial.templatex | 1 + clients/drcachesim/tests/schedule_stats_nopreempt.templatex | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/clients/drcachesim/tests/core_serial.templatex b/clients/drcachesim/tests/core_serial.templatex index 1fdc9b8531..4ad9fe5dfe 100644 --- a/clients/drcachesim/tests/core_serial.templatex +++ b/clients/drcachesim/tests/core_serial.templatex @@ -8,6 +8,7 @@ Total counts: 106490 instructions per context switch 6 voluntary context switches 0 direct context switches + 0 context switch sequence injections 100.00% voluntary switches 0.00% direct switches 4 switches input-to-input diff --git a/clients/drcachesim/tests/schedule_stats_nopreempt.templatex b/clients/drcachesim/tests/schedule_stats_nopreempt.templatex index b04b4d291d..e511c57a31 100644 --- a/clients/drcachesim/tests/schedule_stats_nopreempt.templatex +++ b/clients/drcachesim/tests/schedule_stats_nopreempt.templatex @@ -8,6 +8,7 @@ Total counts: 106490 instructions per context switch 6 voluntary context switches 0 direct context switches + 0 context switch sequence injections 100\.00% voluntary switches 0\.00% direct switches 5 switches input-to-input @@ -45,6 +46,7 @@ Core #0 counts: *[0-9]* instructions per context switch . voluntary context switches 0 direct context switches + 0 context switch sequence injections 100\.00% voluntary switches 0\.00% direct switches .* @@ -56,6 +58,7 @@ Core #1 counts: *[0-9]* instructions per context switch . voluntary context switches 0 direct context switches + 0 context switch sequence injections 100\.00% voluntary switches 0\.00% direct switches .* @@ -67,6 +70,7 @@ Core #2 counts: *[0-9]* instructions per context switch . voluntary context switches 0 direct context switches + 0 context switch sequence injections 100\.00% voluntary switches 0\.00% direct switches .* @@ -78,6 +82,7 @@ Core #3 counts: *[0-9]* instructions per context switch . voluntary context switches 0 direct context switches + 0 context switch sequence injections 100\.00% voluntary switches 0\.00% direct switches .* From 72cc39d2411e0a27782dd8990a5a17959fab75ff Mon Sep 17 00:00:00 2001 From: Abhinav Anil Sharma Date: Tue, 25 Feb 2025 10:42:30 -0500 Subject: [PATCH 3/3] Reviewer suggested edits --- clients/drcachesim/common/memtrace_stream.h | 2 +- clients/drcachesim/scheduler/scheduler_impl.cpp | 2 +- clients/drcachesim/tools/schedule_stats.cpp | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/clients/drcachesim/common/memtrace_stream.h b/clients/drcachesim/common/memtrace_stream.h index 44e48891e3..31d4a6ea50 100644 --- a/clients/drcachesim/common/memtrace_stream.h +++ b/clients/drcachesim/common/memtrace_stream.h @@ -115,7 +115,7 @@ class memtrace_stream_t { /** * Counts the instances when the context switch sequence was injected. */ - SCHED_STAT_SWITCH_SEQUENCE_INJECTIONS, + SCHED_STAT_KERNEL_SWITCH_SEQUENCE_INJECTIONS, /** Count of statistic types. */ SCHED_STAT_TYPE_COUNT, }; diff --git a/clients/drcachesim/scheduler/scheduler_impl.cpp b/clients/drcachesim/scheduler/scheduler_impl.cpp index 1a14d7e364..6516728cf6 100644 --- a/clients/drcachesim/scheduler/scheduler_impl.cpp +++ b/clients/drcachesim/scheduler/scheduler_impl.cpp @@ -2309,7 +2309,7 @@ scheduler_impl_tmpl_t::set_cur_input( // odd to have regular records with the new tid before the top headers. if (!switch_sequence_[switch_type].empty()) { ++outputs_[output] - .stats[memtrace_stream_t::SCHED_STAT_SWITCH_SEQUENCE_INJECTIONS]; + .stats[memtrace_stream_t::SCHED_STAT_KERNEL_SWITCH_SEQUENCE_INJECTIONS]; for (int i = static_cast(switch_sequence_[switch_type].size()) - 1; i >= 0; --i) { RecordType record = switch_sequence_[switch_type][i]; diff --git a/clients/drcachesim/tools/schedule_stats.cpp b/clients/drcachesim/tools/schedule_stats.cpp index abc1ae6e04..fd7b4849bb 100644 --- a/clients/drcachesim/tools/schedule_stats.cpp +++ b/clients/drcachesim/tools/schedule_stats.cpp @@ -168,7 +168,7 @@ schedule_stats_t::get_scheduler_stats(memtrace_stream_t *stream, counters_t &cou stream->get_schedule_statistic(memtrace_stream_t::SCHED_STAT_HIT_OUTPUT_LIMIT)); counters.switch_sequence_injections = static_cast(stream->get_schedule_statistic( - memtrace_stream_t::SCHED_STAT_SWITCH_SEQUENCE_INJECTIONS)); + memtrace_stream_t::SCHED_STAT_KERNEL_SWITCH_SEQUENCE_INJECTIONS)); // XXX: Currently, schedule_stats is measuring swap-ins to a real input. If we // want to match what "perf" targeting this app would record, which is swap-outs,